In integrated circuits, a common feature is a buried contact, which is a contact of a strip of conductive material such as a metal, metal silicide or doped polycrystalline silicon (polysilicon), to a doped semiconductor substrate region, such as a source/drain region or a well region. The typical procedure in the formation of a buried contact first involves the formation of a plurality of field oxide or isolation regions on and in the surface of a doped well or tub of semiconductor material or on the doped surface of the substrate itself. A dielectric material layer, such as silicon dioxide or the like, is next formed over the substrate and contact holes are cut through the dielectric material. Contact to the substrate is achieved by forming a layer of doped polysilicon extending at least part way into or over the hole, and by diffusing impurity atoms from the polysilicon into the substrate to form a doped contact region in the substrate.
However, as very-large-scale-integration (VLSI) devices are made ever smaller and the number of components in a device increase, contacts, such as buried contacts, located on either side of an isolation region must be placed closer together. The close placement of the buried contacts within a device can result in the overlap of the depletion regions associated with the doped contact region of each contact. The overlap of the depletion regions then results in a leakage current between the contacts. This problem is termed lateral punch-through, and may occur in buried contacts doped with either an n-type or a p-type dopant. Lateral punch-through is a particular problem as device features become smaller and the buried contacts are spaced closer together. Vertical punch-through may also occur, as from a buried contact region through a well of opposite conductivity type to the substrate, which is the same conductivity type as the buried contact regions.
Layers or regions of additional doping around doped regions such as the source and drain regions are not unknown, in general. For example, U.S. Pat. No. 4,613,886 discloses six transistor static-random-access-memory (SRAM) cell wherein a field effect transistor is formed in an n-type well region and a diode is made in the p-type drain region. However, buried contacts, present in the six transistor SRAM cell, are not punch-through protected. In addition, counter doped source and drain regions are known, for example as described in U.K. Pat. 2,036,431 wherein heavily doped regions surround the source and drain regions of a metal-oxide-semiconductor (MOS) transistor. The surrounding features taught by the above cited references are within or part of the individual transistors and are not correctly doped to provide any kind of electrical punch-through prevention. Thus, devices of the prior art do not provide the punch-through prevention function for buried contacts associated with separate devices in close proximity to each other.